The present invention relates to a bipolar transistor and method for making same which is self-aligned and capable of being fabricated with small cell size.
The direction of progress in bipolar integrated circuit technology is towards higher levels of integration and greatly reduced transistor cell size. The consequence of reduced cell size is a reduction in the parasitic resistances and capacitances which limit device performance. Since about 1978 various polysilicon self-alignment techniques have been developed in order to achieve such a reduced cell size. While each polysilicon self-aligned device has its own unique characteristics all of them are based on the concept of self-aligning an emitter to an edge of a polysilicon base contacting layer. A common problem with each of these techniques is that a P.sup.+ doped polysilicon layer must be etched or otherwise removed from a single crystalline silicon region in which an emitter is to be subsequently formed. Any defects induced in the emitter area during the P.sup.+ etch or during intermediate processing steps prior to emitter formation will degrade the device characteristics. Consequently, known polysilicon self-aligned processes are very complex.
A Cuthbertson et al. in an article entitled "Self-Aligned Transistors with Polysilicon Emitters for Bipolar VLSI" published in IEEE Trans. Electron Devices, v. ED-32, No. 2, pp 242-247, February, 1985, discloses a transistor structure in which the P.sup.+ inactive base region is self-aligned to a polysilicon emitter and which defines the emitter region early in the fabrication sequence making the emitter less susceptible to surface defects. Furthermore, the single crystal silicon region on which polysilicon is removed is an inactive device area, so dry etch induced damage is less critical. However, in the Cuthbertson et al. transistor, the spacing between the diffused P+ and emitter junctions is defined by thermally oxidizing the edge of the N.sup.+ polysilicon emitter which makes junction depth control very difficult. Moreover, the separation of the P.sup.+ base and N.sup.+ emitter is not sufficient to inhibit the formation of a P.sup.+ N.sup.+ base-emitter junction which degrades the junction breakdown voltage and the low-current characteristics of the device.
Accordingly, it is a principal object of the invention to provide a bipolar transistor structure and method of fabricating such a structure which allows greater size reduction and improved performance than hitherto known structures. It is a further object of the present invention to provide an improved self-alignment method for forming the emitter and extrinsic base regions. Yet another object of the invention is to provide an improved method of forming a diffused collector contact region.